The present invention relates to memory devices and methods of operation thereof, and more particularly, to buffer circuits and methods of operation thereof.
Synchronous dynamic random access memory (SDRAM) devices typically output memory cell data in synchronization with a clock signal in response to an external command, e.g., a read command, that is received in synchronization with an external clock signal. The number of clock cycles occurring between the external command, which is synchronized with the external clock signal, and the output of data, which is synchronized with the clock signal, is often referred to as a latency number.
It may be desirable for an SDRAM device to operate over a range of clock frequencies. The maximum clock frequency of an SDRAM may be constrained by limits on minimum delay, jitter and skew of output data produced by the SDRAM. To increase the operating frequency of the SDRAM, latency in operation of output buffers may be introduced to allow sense amplifiers and other circuitry within the SDRAM to stabilize. However, when an SDRAM that operates with a latency designed for a relatively high clock frequency is operated at a relatively low clock frequency, the latency may introduce unnecessary delay in access time.
FIGS. 1 and 2 illustrates a part of a conventional SDRAM 1 and exemplary operations thereof. Memory cell data is transmitted through an internal circuit 2 to a data line DIO, and on to an output pad DQ via a latch circuit LAT1 and an output buffer 3. The signal applied to the output buffer is delayed by a time Del1, which is predominantly introduced by the internal circuit 2. A data hold signal hold is asserted to a logic high level, so that the memory cell data on the data line DIO is transmitted to the output buffer 3.
Referring to FIG. 2, first, second and third time intervals are defined, each corresponding to approximately a half the clock cycle of a clock signal (CLK). The first, second and third intervals denote latency intervals, i.e., latency may be determined according to which among the first, second and third intervals the delay time Del1 of FIG. 1 falls, with the first interval representing a latency of 1, the second interval representing a latency of 1.5, and the third interval representing a latency of 2. For example, as shown in FIG. 2, memory cell data having a delay time Del1 falling within the third interval following the rising edge of the clock signal CLK that coincides with a data read command READ is transmitted to the data line DIO with a latency of 2. Accordingly, valid data of the memory cell data is output to the output pad DQ two clock cycles after the rising edge of the clock signal CLK that coincides with the data read command READ.
Still referring to FIG. 2, if the SDRAM 1 that operates with a latency of 2 for a relatively high frequency clock CLK as described above is used with a lower clock frequency CLK_1, however, memory cell data which has passed through the internal circuit block 2 arrives at the data line DIO delayed by the delay time Del1 after the rising edge of a clock signal CLK_1 that coincides with the data read command READ. Under these conditions, a time loss T.sub.LOSS with respect to the operation with the higher frequency clock signal CLK may be incurred. This may degrade operating performance.